1. Field of the Invention
The invention concerns a new organic transistor and a method for making the same.
2. Related Technology
Field-effect transistors (FETs), are three-terminal devices that comprise a source contact, a drain contact, and a gate contact. According to a basic structure, a semiconductive layer bridges the source and drain contacts, and is itself spaced from the gate contact by an insulating layer called the gate dielectric. In the on state, a “channel” is created in the semiconductive layer through which charges pass from the source electrode to the drain electrode. In organic transistors, the semiconductive layer is fabricated from a semiconductive organic material. In particular, in polymer transistors, the semiconductive organic layer is fabricated from a semiconductive polymer, typically a n-conjugated organic polymer. This layer may be deposited in the device by a precursor route or directly by solution processing.
A voltage is applied across the source contact and the drain contact. Further, in a field effect transistor, a voltage is applied to the gate contact. This voltage creates a field that alters the current-voltage characteristics of the semiconductive layer by causing accumulation or depletion of charge carriers there. This in turn modulates the channel resistance and the rate at which charges pass from the source to the drain contact (that is, the source-drain current) for a given source-drain voltage.
In principle, organic field effect transistors (FETs) can operate in two modes; either as an n-channel device (where the charges accumulated in the channel are electrons) or a p-channel device (where the charges accumulated in the channel are holes).
Organic field effect transistors (FETs) can be fabricated in two configurations: a top-gate configuration or a bottom gate configuration.
FETs having a multilayer device structure, with layers beyond the basic structure outlined above, are known from WO 01/47043, WO 01/47044, WO 01/047045, and WO 01/46987.
WO 01/47043 is concerned with solution processed transistors. A method is provided for forming a transistor comprising depositing a first material from solution using a first solvent to form a first layer of the transistor; and subsequently while the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble. The method maintains the integrity of the layer sequence during device manufacture.
WO 01/47044 is concerned, in one aspect, with locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layers; and depositing conductive or semiconductive material in the void. It is said that the material deposited in the void may form a via hole interconnect between electrodes and/or interconnect lines in different layers of the device. In another aspect, WO 01/47044 discloses locally depositing a diffusive dopant from solution at a localised region of the insulating layer so as to modify the insulating and semiconductive layers in the region and thereby form a channel of electrically conductive material extending through the sequence of layers. Again it is said that the channel may form a via hole interconnect between electrodes and/or interconnect lines in different layers of the device.
WO 01/47045 is concerned with a confinement technique which can be used to permit fine resolution deposition of a deposited material onto a substrate. In particular, the confinement technique is disclosed for forming the source and drain electrodes of a transistor.
WO 01/46987 is concerned with forming at least part of a transistor by ink jet printing.
All of WO 01/47043, WO 01/47044, WO 01/047045, and WO 01/46987 disclose a transistor having the basic structure defined above. That is to say, the transistors have a source contact, a drain contact, a gate contact, a semiconductive layer, and an insulating layer. It is further said that the devices may include an isolation layer. The isolation layer may provide a diffusion barrier and/or a surface modification layer. The diffusion barrier layer protects the semiconducting layer and the insulating layer against unintentional doping by impurities and ionic diffusion. The ionic impurities are believed to originate from the PEDOT gate electrode. The surface modification layer enables high resolution patterning of the gate electrode by printing techniques. According to page 10 of WO 01/47043, the isolation layer is between the insulator and the gate electrode.
The device structures according to FIG. 1 of WO 01/47043 show a diffusion barrier layer (7) and a surface modification layer (8) between the insulating layer (5) and the gate electrode (6) for a device in top gate configuration. The device structure shown in FIG. 17 shows a diffusion barrier layer (7) and a surface modification layer (8) between the insulating layer (5) and source-drain electrodes (2), (3) and the semiconducting layer (4) for a device in bottom gate configuration.
An alignment layer also is disclosed in WO 01/47043, WO 01/47044, WO 01/047045, WO 01/46987, and WO 00/79617 such as a mechanically rubbed polyimide layer. The alignment layer is coated on the glass substrate prior to depositing the semiconducting polymer layer. The alignment layer is used to align the polymer chains of the semiconducting polymer to improve charge carrier mobility.
It is also disclosed that to achieve high current switching ratios it is important that a polymer semiconductor is used with good stability against unintentional doping by oxygen or water during device manufacture. Thus, the desirability of a high switching ratio (on-off current ratio) is mentioned in WO 01/47043, WO 01/47044, WO 01/047045, and WO 01/46987. The on-off current ratio is the ratio between the current in the on state (the on current) and the current in the off state (the off current). A high on-off current ratio means there is a good difference between the on state and the off state of the device, which means better switching characteristics of the device. A low on-off current ratio means that it is difficult to turn the transistor off because current passes between the source and drain in the off state. It may also be difficult to turn the transistor on because a low mobility semiconductor means that little current is passed in the on-state. To maximise the on-off current ratio, the off current should be low and the on current should be high. One possibility known in the art for increasing the on current is to use a semiconducting material having a high mobility. According to WO 01/47043, WO 01/47044, WO 01/047045, and WO 01/46987, TFB is a suitable material for use as the semiconducting polymer (see for example page 6 of WO 01/47043).
The PhD thesis of Richard Wilson (University of Cambridge, 2003) shows that a TFB single layer device with gold source and drain electrodes is not commercially viable since TFB has too low a charge carrier mobility. However, this thesis also shows that the gold source and drain electrodes form resistive contacts to TFB.